Functional Verification of Programmable Embedded Architectures : A Top-Down Approach

Contents: Preface. Acknowledgements. I. Introduction to functional verification: 1. Introduction. II. Architecture specification: 2. Architecture specification. 3. Validation of specification. III. Top-down validation: 4. Executable model generation. 5. Design validation. 6. Functional test generation. IV. Future directions: 7. Conclusions. V. Appendices: i. Survey of contemporary ADLs. ii. Specification of DLX processor. iii. Interrupts and exceptions in ADL. iv. Validation of DLX specification. v. Design space exploration. References. Index. 

"Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-On-Chip Design Methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models.

This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architecture\'s knowledge about the behaviour of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric." (jacket)